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SAA7111A Datasheet(PDF) 7 Page - NXP Semiconductors |
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SAA7111A Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 72 page  1998 May 15 7 Philips Semiconductors Product specification Enhanced Video Input Processor (EVIP) SAA7111A RTS0 29 O Two functions output; controlled by I2C-bus bit RTSE0. RTSE0 = 0: odd/even field identification (HIGH = odd field). RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) has locked. VS 30 O Vertical sync signal (enabled via I2C-bus bit OEHV); this signal indicates the vertical sync with respect to the YUV output. The HIGH period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deflection controller. HREF 31 O Horizontal reference output signal (enabled via I2C-bus bit OEHV); this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is 720 Y samples long. HREF can be used to synchronize data multiplexer/demultiplexer. HREF is also present during the vertical blanking interval. VSSD3 32 P Ground for digital supply voltage input 3. VDDD3 33 P Digital supply voltage 3 (+3.3 V). VPO (15 to 10) 34 to 39 O Digital VPO-bus (Video Port Out) signal; higher bits of the 16-bit VPO-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing scheme of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the six MSBs of the digitized input signal are connected to these outputs, configured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0. VSSD2 40 P Ground for digital supply voltage input 2. VDDD2 41 P Digital supply voltage 2 (+3.3 V). VPO (9 to 0) 42 to 51 O Digital VPO-bus output signal; lower bits of the 16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data rate, the format and multiplexing schema of the VPO-bus are controlled via I2C-bus bits OFTS0 and OFTS1. If I2C-bus bit VIPB = 1 the digitized input signal are connected to these outputs, configured by the I2C-bus ‘MODE’ bits (see Figs 33 to 40): LUMA → VPO15 to VPO8, CHROMA → VPO7 to VPO0. FEI 52 I Fast enable input signal (active LOW); this signal is used to control fast switching on the digital YUV-bus. A HIGH at this input forces the IC to set its Y and UV outputs to the high impedance state. GPSW 53 O General purpose switch output; the state of this signal is set via I2C-bus control and the levels are TTL compatible. XTAL 54 O Second terminal of crystal oscillator; not connected if external clock signal is used. XTALI 55 I Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator with CMOS compatible square wave clock signal. VSSD1 56 P Ground for digital supply voltage input 1. VDDD1 57 P Digital supply voltage input 1 (+3.3 V). TRST 58 I Test reset input not (active LOW), for boundary scan test; notes 1, 2 and 3. TCK 59 I Test clock for boundary scan test; note 1. RTCO 60 O Real time control output: contains information about actual system clock frequency, subcarrier frequency and phase and PAL sequence. SYMBOL PIN I/O/P DESCRIPTION (L)QFP64 |
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