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RF3802
Rev A6 050609
Thermal Pad and Via Design
The DUT must be connected to the PCB backside ground through a low inductance, low thermal resistance path. The
required interface is achieved with the via pattern shown below for both low inductance as well as low thermal resistance.
The footprint provided below worked well on the RFMD 20mil thick Rogers 4350 PCB and also standard FR4. The vias
are 8mil vias that are partially plated through and are finished to 8mils±2mils with a minimum plating of 1.5mil. Failure to
place these vias within the DUT mounting area on the PCB in this prescribed manner may result in electrical perfor-
mance and/or reliability degradation.
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