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SP6203EM5-2-8 Datasheet(PDF) 11 Page - Sipex Corporation |
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SP6203EM5-2-8 Datasheet(HTML) 11 Page - Sipex Corporation |
11 / 16 page Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation Date: 2//05 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2005 Sipex Corporation Note that the regulator cannot always be used at its maximum current rating. For example, in a 5V input to 3.0V output application at an ambi- ent temperature of 25°C and operating at the full 500mA (IGND = 0.355mA) load, the regulator is limited to a much lower load current, deter- mined by the following equation: 523mW = ( [5V-3V]*[ Iload(max)]) +(5V*0.350mA) After calculation, we find that in such an appli- cation (SP6205) the regulator is limited to 260.6mA. Doing the same calculations for the 300mA LDO (SP6203) will limit the regulator’s output current to 260.9mA. Also, taking advantage of the very low dropout voltage characteristics of the SP6203/6205, power dissipation can be reduced by using the lowest possible input voltage to minimize the input-to-output drop. Adjustable Regulator Applications The SP6203/6205 can be adjusted to a specific output voltage by using two external resistors (see functional diagram). The resistors set the output voltage based on the following equation: VOUT = VREF *(R1/R2 + 1) Resistor values are not critical because ADJ (adjust) has a high input impedance, but for best performance use resistors of 470K or less. A bypass capacitor from ADJ to VOUT provides improved noise performance. Dual-Supply Operation When used in dual supply systems where the regulator load is returned to a negative supply, the output voltage must be diode clamped to ground. Layout Considerations The primary path of heat conduction out of the package is via the package leads. Therefore, careful considerations have to be taken into account: 1) Attaching the part to a larger copper footprint will enable better heat transfer from the device, especially on PCB’s where there are internal ground and power planes. 2) Place the input, output and bypass capacitors close to the device for optimal transient re- sponse and device behavior. 3) Connect all ground connections directly to the ground plane. In case there’s no ground plane, connect to a common local ground point before connecting to board ground. Such layouts will provide a much better thermal conductivity (lower JA) for, a higher maximum allowable power dissipation limit. THEORY OF OPERATiON: Continued |
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