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SP333CT Datasheet(PDF) 4 Page - Sipex Corporation |
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SP333CT Datasheet(HTML) 4 Page - Sipex Corporation |
4 / 13 page 4 Rev 07/29/02 SP333 RS-232/AppleTalk Programmable Transceiver © Copyright 2002 Sipex Corporation SPECIFICATIONS (CONTINUED) T MIN to TMAX and VCC = 5V±5% unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-232 Receiver Low Threshold 0.8 1.2 Volts Input Voltage Range -15 +15 Volts Input Impedance 3 5 7 kOhms V IN=±15V Hysteresis 0.2 0.5 1.0 Volts V CC=+5V Transmission Rate 10 Mbps Propagation Delay t PHL 100 600 ns From 50% of V IN to 1.5V of ROUT t PLH 100 600 ns From 50% of V IN to 1.5V of ROUT Data Rate 460 600 kbps POWER REQUIREMENTS No Load Supply Current 15 25 mA No load; V CC=5.0V; TA=25˚C Shutdown Supply Current 75 µAT A=25˚C, VCC=5.0V AC PARAMETERS Differential Mode t PZL; Enable to Output low 200 1000 ns C L=100pF, Figures 2 & 4, S2 closed t PZH; Enable to Output high 200 1000 ns C L=100pF, Figures 2 & 4, S1 closed t PLZ; Disable from Output low 200 1000 ns C L=15pF, Figures 2 & 4, S2 closed t PHZ; Disable from Output high 200 1000 ns C L=15pF, Figures 2 & 4, S1 closed Receiver Delay Time from Enable Mode to Tri-state Mode Single-Ended Mode t PZL; Enable to Output low 200 1000 ns C RL=15pF, Figures 1 & 6, S1 closed t PZH; Enable to Output high 200 1000 ns C RL=15pF, Figures 1 & 6, S2 closed t PLZ; Disable from Output low 200 1000 ns C RL=15pF, Figures 1 & 6, S1 closed t PHZ; Disable from Output high 200 1000 ns C RL=15pF, Figures 1 & 6, S2 closed Differential Mode t PZL; Enable to Output low 200 1000 ns C RL=15pF, Figures 1 & 6, S1 closed t PZH; Enable to Output high 200 1000 ns C RL=15pF, Figures 1 & 6, S2 closed t PLZ; Disable from Output low 200 1000 ns C RL=15pF, Figures 1 & 6, S1 closed t PHZ; Disable from Output high 200 1000 ns C RL=15pF, Figures 1 & 6, S2 closed Notes: 1. Measured from 2.5V of R IN to 2.5V of ROUT. 2. Measured from one–half of R IN to 2.5V of ROUT. 3. Measured from 1.5V of T IN to one–half of TOUT. 4. Measured from 2.5V of R O to 0V of A and B. 500Ω CL Output Under Test S1 S2 VCC 1KΩ 1KΩ CRL Receiver Output S1 S2 Test Point VCC Figure 2. Receiver Timing Test Load Circuit Figure 1. Driver Timing Test Load Circuit |
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