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SAA4945H Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA4945H Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 20 page 1997 Jun 10 8 Philips Semiconductors Preliminary specification LIne MEmory noise Reduction IC (LIMERIC) SAA4945H Table 8 Input /output data coding INPUT BIT INPUT DATA SEQUENCE YY7 Y07Y17Y27Y37 Y6 Y06Y16Y26Y36 Y5 Y05Y15Y25Y35 Y4 Y04Y14Y24Y34 Y3 Y03Y13Y23Y33 Y2 Y02Y12Y22Y32 Y1 Y01Y11Y21Y31 Y0 Y00Y10Y20Y30 U UI1 U07U05U03U01 UI0 U06U04U02U00 V VI1 V07V05V03V01 VI0 V06V04V02V00 WEI (PIN 21) • Write enable input • Write enable indicates the time when active input samples (Y, U and V) are present • Timing relation (see Fig.4) depending on the logic level of the Write Enable Select signal (WES) in status register; to adapt to different external video memories • The number of input samples is a multiple of 4 (see Fig.4) • Start of new line indicated by write enable signal LOW for at least 4 consecutive clock periods (see Fig.4) • During active line, WE I is not allowed to be LOW for more than 1 clock cycle. |
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