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XRK4991A Datasheet(PDF) 1 Page - Exar Corporation |
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XRK4991A Datasheet(HTML) 1 Page - Exar Corporation |
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Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FEBRUARY 2005 REV. P1.0.2 FUNCTIONAL DESCRIPTION The XRK4991A 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50 Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability is combined with the selectable output skew functions, the user can create output-to- output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low- frequency clock that can be multiplied by two or four at the clock destination. This feature minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. FEATURES • Ref input is 5V tolerant • 3 pairs of programmable skew outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • Synchronous output enable • Output frequency: 3.75MHz to 85MHz • 2x, 4x, 1/2, and 1/4 outputs • 2 skew grades • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • 32-pin PLCC package • Jitter < 200 ps peak-to-peak (< 25 ps RMS) • Green packaging FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A VCO AND TIME UNIT GENERATOR SKEW SELECT MATRIX PHASE FREQ DET FILTER FB_IN CLKIN FSEL SELD0 TEST QD0 QD1 QC0 QC1 QB0 QB1 QA0 QA1 Select Inputs SELA1 SELA0 SELB1 SELB0 SELC1 SELC0 SELD1 0E PE |
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