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XRK4991A Datasheet(PDF) 3 Page - Exar Corporation

Part No. XRK4991A
Description  3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
Download  13 Pages
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
Logo EXAR - Exar Corporation

XRK4991A Datasheet(HTML) 3 Page - Exar Corporation

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PRELIMINARY
XRK4991A
REV. P1.0.2
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
3
PIN DESCRIPTIONS
PIN NAME
PIN #
TYPE
DESCRIPTION
CLKIN
1
I
Reference frequency input. This input supplies the frequency and timing against
which all functional variation is measured.
FB_IN
17
I
PLL feedback input (typically connected to one of the eight outputs).
FSEL
3
I
Three-level frequency range select. Set Table 2.
SELA0
SELA1
26
27
I
Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3.
SELB0
SELB1
29
30
I
Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3.
SELC0
SELC1
4
5
I
Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3.
SELD0
SELD1
7
1
I
Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3.
TEST
31
I
Three-level select. See test mode section under the block diagram descriptions.
OE
28
I
Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0])
in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase
lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for
normal operation.
PE
8
I
Selectable positive or negative edge control. When "Low"/"High" the outputs are
synchronized with the negative/positive edge of the reference clock.
QA0
QA1
24
23
O
Output pair 1. See Table 2.
QB0
QB1
20
19
O
Output pair 2. See Table 2.
QC0
QC1
15
14
O
Output pair 3. See Table 2.
QD0
QD1
11
10
O
Output pair 4. See Table 2.
VCCN
9
16
18
25
PWR
Power supply for output drivers.
VCCQ
2
PWR
Power supply for internal circuitry.
GND
12
13
21
22
32
PWR
Ground.


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