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SAA2023GP Datasheet(PDF) 11 Page - NXP Semiconductors |
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SAA2023GP Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 56 page  May 1994 11 Philips Semiconductors Preliminary specification Drive processor for DCC systems SAA2023 Table 7 Digital equalizer register names. REGISTER NAME READ/WRITE CMD W STATUS0 R STATUS1 R COEFCNT W FCTRL W CHT1SEL W CHT2SEL W ANAEYE W AEC R/W SSPD R INTMASK W DEQ2SET W CLKSET W DATA STREAMS The digital equalizer module has one write only and one read only data stream that are accessible via the L3 interface and they are shown in Table 8. Table 8 Digital equalizer data streams. DIGITAL EQUALIZER “COMMANDS” These are the commands that need to be sent to the digital equalizer in order to access the indirectly accessible registers and the data streams. DATA STREAM NAME READ/WRITE FIR coefficients to buffer bank W FIR coefficients from active bank W Table 9 Digital equalizer commands. Table 10 Filter control register. Note 1. µCS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient number 9 has been received. NAME COMMAND BYTE EXPLANATION 76543210 WRCOEF 00110000 write FIR coefficients to the digital equalizer buffer bank RDCOEF 00100000 read FIR coefficients from the digital equalizer active bank LDCOEFCNT 00010011 load FIR coefficient counter LDFCTRL 00010100 load filter control register LDT1SEL 00010110 load CHTST1 pin selection register LDT2SEL 00010111 load CHTST2 pin selection register LDTAEYE 00011000 load ANAEYE channel selection register LDAEC 00011001 load AEC counter RDAEC 00100010 read AEC counter RDSSPD 00100100 read SEARCH speed register LDINTMSK 00010010 load interrupt mask register LDDEQ3SET 00010000 load digital equalizer settings register LDCLKSET 00010001 load PLL clock extraction settings register BIT 765432 1 0 Meaning −−− µCS(1) SH1 SH0 Reserved Default 0 0 0 0 1 0 1 1 |
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