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XR88C92 Datasheet(PDF) 11 Page - Exar Corporation |
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XR88C92 Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 32 page  XR88C92/192 11 Rev. 1.33 framing error, and received-break conditions are the logical OR of these respective bits, for all the data bytes in the FIFO stack since the last reset error command (see CRA, CRB bits 7:4) was issued. That is, beginning immediately after the last reset-error command was issued, a continuous logical-OR function of corre- sponding status bits is produced in the status register as each character enters the FIFO. The block mode is useful in applications requiring the exchange of blocks of information where the software overhead of checking each character's error flags can- not be tolerated. In this mode, entire messages can be received and only one data integrity check is performed at the end of each message. Although data reception in this manner has speed advantages, there are also disadvantages. If an error occurs within a message the error will not be recognized until the final check is performed. Also, there is no indication of which character(s) is in error within the message. Reading the status register (SRA, SRB) does not affect the FIFO. The FIFO is “popped” only when the receive buffer is read. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exists, the con- tents of the FIFO are not affected, but the character previously in the shift register is lost and the overrun- error status bit will be set upon receipt of the start bit of the new overrunning character. To support flow control, a receiver can automatically negate and reassert the request-to-send (RTS) output (RX RTS control - see MR1A, MR1B bit-7). The request- to-send output (at OP0 or OP1 for channel A or B respectively) will automatically be negated by the re- ceiver when a valid start bit is received and the FIFO stack is full. When a FIFO position becomes available, the request-to-send output will be reasserted automati- cally by the receiver. Connecting the request-to-send output to the clear-to send (CTS) input of a transmitting device prevents overrun errors in the receiver. The RTS output must be manually asserted the first time. There- after, the receiver will control the RTS output. If the FIFO stack contains characters and the receiver is then disabled, the characters in the stack can still be read but no additional characters can be received until the receiver is again enabled. If the receiver is disabled while receiving a character, or while there is a character in the shift register waiting for a FIFO opening, these characters are lost. If the receiver is reset, the FIFO stack and all of the receiver status bits, the correspond- ing output ports, and the interrupt request are reset. No additional characters can be received until the receiver is again enabled. LOOPBACK MODES Besides the normal operation mode in which the re- ceiver and transmitter operate independently, each XR88C92/192 channel can be configured to operate in various looping modes (see MR2A, MR2B bits 7:6) that are useful for local and remote system diagnostic functions. AUTOMATIC ECHO MODE In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to- receiver communication continues normally but the CPU-to-transmitter link is disabled. LOCAL LOOPBACK MODE In this mode, the transmitter output is internally con- nected to the receiver input. The external TX pin is held in the mark (high) state in this mode. By sending data to the transmitter and checking that the data assembled by the receiver is the same data that was sent, proper channel operation can be assured. In this mode the CPU-to-transmitter and CPU-to-receiver communica- tions continue normally. REMOTE LOOPBACK MODE In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU-to- receiver and CPU-to-transmitter links are disabled. This mode is useful in testing the receiver and transmitter operation of a remote channel. This mode requires the remote channel receiver to be enabled. MULTIDROP MODE - Enhanced with Extra A/D Tag Storage Users can program the channel to operate in a wake- up mode for Multidrop applications. In this mode of operation (set MR1A, MR1B bits 4:3 = 11), the XR88C92/192, as a master station channel connected to several slave stations (a maximum of 256 unique slave stations), transmits an address character fol- lowed by a block of data characters targeted for one or more of the slave stations. The channel receivers within the slave stations are disabled, but they continuously monitor the data stream sent out from the master |
Similar Part No. - XR88C92_05 |
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Similar Description - XR88C92_05 |
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