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XR20V2170IL40 Datasheet(PDF) 10 Page - Exar Corporation |
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XR20V2170IL40 Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 52 page  XR20V2170 10 I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER REV. 1.0.0 2.6 Crystal Oscillator or External Clock Input The V2170 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.7, Programmable Baud Rate Generator with Fractional Divisor” on page 10.” The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 7). The programmable Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. Although the V2170 can accept an external clock of up to 64MHz, the maximum data rate supported by the RS-232 drivers is 250Kbps. For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.7 Programmable Baud Rate Generator with Fractional Divisor Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the TABLE 5: IRQ# PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) IRQ# Pin HIGH = no data LOW = 1 byte HIGH = FIFO below trigger level LOW = FIFO above trigger level FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS C1 22-47 pF C2 22-47 pF Y1 1.8432 MHz to 24 MHz R1 0-120 Ω (Optional) R2 500ΚΩ−1ΜΩ XTAL1 XTAL2 |
Similar Part No. - XR20V2170IL40 |
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Similar Description - XR20V2170IL40 |
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