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SAA1057 Datasheet(PDF) 8 Page - NXP Semiconductors |
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SAA1057 Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 13 page  November 1983 8 Philips Semiconductors Product specification Radio tuning PLL frequency synthesizer SAA1057 Set-up time for DATA to CLB tDATAlead 2 −− µs Hold time for DATA to CLB tDATAhold 0 −− µs Hold time for DLEN to CLB tDLENhold 2 −− µs Set-up time for DLEN to CLB load pulse tCLBlag2 2 −− µs Busy time from load pulse next transmission after word ‘B’ to other device to next start of transmission tDIST 5 −− µs Busy time or asynchronous mode tDIST 0,3 −− ms next transmission to SAA1057 after word ‘A’ (see also note 5) synchronous mode tDIST 1,3 −− ms Sample and hold circuit (TR, TCA, TCB) see also notes 3; 4 Minimum output voltage VTCA, VTCB − 1,3 − V Maximum output voltage VTCA, VTCB −− VCC2−0,7 V Capacitance at TCA CTCA −− 2,2 nF REFH = ‘1’ (external) CTCA −− 2,7 nF REFH = ‘0’ Discharge time at TCA tdis −− 5 µs REFH = ‘1’ tdis −− 6,25 µs REFH = ‘0’ Resistance at TR RTR 100 −− Ω external Voltage at TR during discharge VTR − 0,7 − V Capacitance at TCB CTCB −− 10 nF external Bias current into TCA, TCB Ibias −− 10 nA in-lock Programmable current amplifier (PCA) Output current of the dig. phase detector ± Idig − 0,4 − mA Current gain of PCA CP3 CP2 CP1 CP0 P1 0 0 0 0 GP1 − 0,023 − VCC2 ≥ 5 V (only for P1) P2 0 0 0 1 GP2 − 0,07 − P3 0 0 1 0 GP3 − 0,23 − P4 0 1 1 0 GP4 − 0,7 − P5 1 1 1 0 GP5 − 2,3 − SYMBOL MIN. TYP. MAX. CONDITIONS |
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Similar Description - SAA1057 |
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