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XR16L2752IJ Datasheet(PDF) 11 Page - Exar Corporation |
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XR16L2752IJ Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 49 page  xr XR16L2752 REV. 1.2.1 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 11 2.12 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 2.12.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.12.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1 divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0 TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK OUTPUT Data Rate MCR Bit-7=1 OUTPUT Data Rate MCR Bit-7=0 (DEFAULT) DIVISOR FOR 16x Clock (Decimal) DIVISOR FOR 16x Clock (HEX) DLM PROGRAM VALUE (HEX) DLL PROGRAM VALUE (HEX) DATA RATE ERROR (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 C0 00 C0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0C 00 0C 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 |
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