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XR16L580 Datasheet(PDF) 4 Page - Exar Corporation |
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XR16L580 Datasheet(HTML) 4 Page - Exar Corporation |
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4 / 52 page  XR16L580 4 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PIN DESCRIPTIONS Pin Descriptions NAME 24- QFN PIN# 28- QFN PIN# 32- QFN PIN# 48- TQFP PIN# TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 14 15 16 16 17 18 17 18 19 26 27 28 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transac- tion. D7 D6 D5 D4 D3 D2 D1 D0 4 3 2 24 23 22 21 20 4 3 2 28 27 26 25 24 5 4 3 1 32 31 30 29 4 3 2 47 46 45 44 43 I/O Data bus lines [7:0] (bidirectional). IOR# (NC) 13 13 14 19 I When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge insti- gates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the ris- ing edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used. IOW# (R/W#) 11 11 12 16 I When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. CS# 7 7 8 11 I This input is chip select (active low) to enable the device. INT (IRQ#) 17 19 20 30 O (OD) When 16/68# pin is at logic 1 for Intel bus interface, this output become the active high device interrupt output. The output state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes the active low device interrupt output (open drain). An external pull-up resistor is required for proper operation. MODEM OR SERIAL I/O INTERFACE TX 6 6 7 8 O UART Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0. If it is not used, leave it unconnected. |
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