XRK39351

xr

3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

REV. 1.0.0

4

a. VCMR is the cross point of the differential input signal.

01

REF_SEL

PECL clock inputs selected as reference

TCLK input selected as reference

0

PLL_EN

PLL is bypassed. Test Mode. TCLK refer-

ence source drives the divider select blocks

PLL enabled. Normal operation. VCO out-

put drives the divider select blocks

1

SELA

Bank A divider = 2

Bank A divider = 4

0

SELB

Bank B divider = 4

Bank B divider = 8

0

SELC

Bank C divider = 4

Bank C divider = 8

0

SELD

Bank D divider = 4

Bank D divider = 8

0

OE

Outputs enabled

Outputs tri-stated, VCO running at minimum

frequency

0

a

PECL Clock inputs common mode range

1.2

V

PECL Clock peak-to-peak input voltage

500

1000

mV

Input voltage high

2.0

VCC+0.3

V

Input voltage low

0.8

V

2.4

V

0.55

0.30

V

V

Output Impedance

14-17

Ω

Input leakage current

+150

μΑ

Maximum PLL supply current

3.0

5.0

mA

Maximum Quiescent supply current

4

mA

Output Termination Voltage

V