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XRT79L71 Datasheet(PDF) 6 Page - Exar Corporation |
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XRT79L71 Datasheet(HTML) 6 Page - Exar Corporation |
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6 / 109 page  XRT79L71 II 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE REV. 1.0.0 CHANNEL FRAMER WITH LIU IC (SEE 79L71-REGISTER/MAP-DESC.PDF) ..................................80 6.0 PIN DESCRIPTIONS (SEE 79L71-HARDWARE-MANUAL.PDF) .......................................................80 7.0 ELECTRICAL CHARACTERISTICS (SEE 79L71-HARDWARE-MANUAL.PDF) ...............................80 8.0 MICROPROCESSOR INTERFACE (SEE 79L71-HARDWARE-MANUAL.PDF) ................................80 9.0 ARCHITECTURAL/FUNCTIONAL DESCRIPTION OF THE XRT79L71 1-CHANNEL DS3/E3 ATM UNI/ PPP/CLEAR-CHANNEL FRAMER WITH LIU IC - CLEAR CHANNEL FRAMER AND HIGH-SPEED HDLC CONTROLLER MODE APPLICATIONS (SEE 79L71-CC-ARC-DESC.PDF) ......................................80 10.0 ELECTRICAL CHARACTERISTICS ..................................................................................................81 10.1 DC ELECTRICAL .......................................................................................................................................... 81 TABLE 7: DC ELECTRICAL CHARACTERISTICSS..................................................................................................................... 81 Applies to all TTL-Level Input and CMOS Level Output pins - Ambient Temperature = 25°C .................................. 81 10.2 AC ELECTRICAL CHARACTERISTIC INFORMATION .............................................................................. 81 11.0 MICROPROCESSOR INTERFACE ....................................................................................................81 MICROPROCESSOR INTERFACE TIMING FOR REVISION A SILICON ......................................................81 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS INTEL MODE.................................................... 81 FIGURE 6. ASYNCHRONUS MODE 1 - INTEL TYPE PROGRAMMED I/O TIMING (WRITE CYCLE) ............................................................ 81 FIGURE 7. ASYNCHRONUS MODE 1 - INTEL TYPE PROGRAMMED I/O TIMING (READ CYCLE) ............................................................. 82 TABLE 8: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE INTEL ASYNCHRONOUS MODE ............................................................................................................................................................................ 82 MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE................................................................................................................................83 FIGURE 8. ASYNCHRONUS MODE 2 - MOTOROLA 68K PROGRAMMED I/O TIMING (WRITE CYCLE) .................................................... 83 FIGURE 9. ASYNCHRONUS MODE 2 - MOTOROLA 68 PROGRAMMED I/O TIMING (READ CYCLE) ........................................................ 83 TABLE 9: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE WHEN CONFIGURED TO OPERATE IN THE MOTOROLA (68K) ASYN- CHRONOUS MODE........................................................................................................................................................... 84 MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE84 FIGURE 10. SYNCHRONOUS MODE 3 - IBM POWERPC 403 INTERFACE TIMING (WRITE CYCLE) ....................................................... 84 FIGURE 11. SYNCHRONOUS MODE 3 - IBM POWERPC 403 INTERFACE TIMING (READ CYCLE)......................................................... 85 TABLE 10: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE IBM POWER PC403 MODE ............................................................................................................................................................................ 85 MICROPROCESSOR INTERFACE TIMING - IDT3051/52 MODE ..................................86 FIGURE 12. SYNCHRONOUS MODE 4 - IDT 3051/52 INTERFACE TIMING (WRITE CYCLE) .................................................................. 86 FIGURE 13. SYNCHRONOUS MODE 4 - IDT 3051/52 INTERFACE TIMING (READ CYCLE).................................................................... 87 TABLE 11: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE IBM POWER PC403 MODE ............................................................................................................................................................................ 87 DS3/E3 LIU INTERFACE - LINE SIDE ELECTRICAL CHARACTERISTIC INFORMATION 88 E3 LINE SIDE PARAMETERS .........................................................................................................................88 FIGURE 14. PULSE MASK FOR E3 (34.368MBPS) INTERFACE AS PER ITU-T G.703 ......................................................................... 88 TABLE 12: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS...................................................... 88 DS3 LINE SIDE PARAMETERS .......................................................................................................................89 FIGURE 15. BELLCORE GR-499-CORE PULSE TEMPLATE REQUIREMENTS FOR DS3 APPLICATIONS................................................ 89 TABLE 13: DS3 PULSE MASK EQUATIONS ...................................................................................................................................... 90 TABLE 14: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ............................... 90 TRANSMIT UTOPIA INTERFACE....................................................................................91 FIGURE 16. TIMING DIAGRAM FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ................................................................................ 91 TABLE 15: TIMING INFORMATION FOR THE TRANSMIT UTOPIA INTERFACE BLOCK ........................................................................... 91 TRANSMIT PAYLOAD DATA INPUT INTERFACE.........................................................92 TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS .....................................92 TABLE 16: TIMING INFORMATION FO RTHE TRNASMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................ 92 FIGURE 17. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3 AND LOOP-TIMING MODES .............................................................................................................................................. 93 FIGURE 18. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3 AND LOCAL-TIMING MODES ............................................................................................................................................. 94 FIGURE 19. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/ NIBBLE-PARALLEL AND LOOP-TIMING MODES .................................................................................................................. 94 FIGURE 20. TIMING DIAGRAM FOR THE TRANSMIT PAYLOAD DATA INPUT INTERFACE WHEN THE XRT79L71 IS OPERATING IN BOTH THE DS3/ NIBBLE-PARALLEL AND LOCAL-TIMING MODES ................................................................................................................. 95 TRANSMIT OVERHEAD DATA INPUT INTERFACE ......................................................96 TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS ..................................96 |
Similar Part No. - XRT79L71 |
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Similar Description - XRT79L71 |
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