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XRT75R03D Datasheet(PDF) 50 Page - Exar Corporation |
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XRT75R03D Datasheet(HTML) 50 Page - Exar Corporation |
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50 / 135 page  XRT75R03D 46 THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER REV. 1.0.4 6.2 Clock and Data Recovery: The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: Training Mode: In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the RLOL_n bit to “1” in the control registers (in Host Mode). Also, the clock output on the RxClk_n pins are the same as the reference clock applied on ExClk_n pins. Data/Clock Recovery Mode: In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the RxClk_n out pins is the Recovered Clock signal. FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3. TABLE 9: INTERFERENCE MARGIN TEST RESULTS MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE E3 0 dB Equalizer “IN” -17 dB 12 dB -14 gB DS3 0 feet -15 dB 225 feet -15 dB 450 feet -14 dB STS-1 0 feet -15 dB 225 feet -14 dB 450 feet -14 dB Noise Generator 2 23 -1 PRBS Signal Source N S Attenuator 1 Attenuator 2 ∑ Test Equipment Cable Simulator DUT XRT75R03D |
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