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XR16V2751 Datasheet(PDF) 7 Page - Exar Corporation |
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XR16V2751 Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 52 page  XR16V2751 7 REV. 1.0.0 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 1.0 PRODUCT DESCRIPTION The XR16V2751 (V2751) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the XR16V2750 and XR16C2850 devices but offers Intel or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode. Hence, the V2751 adds 4 more inputs: 16/68#, PwrSave, HDCNTL# and CLKSEL pins. Each UART is independently controlled having its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/ Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4. The XR16V2751 can operate from 2.25V to 3.6V with 5 volt tolerant inputs. The V2751 is fabricated with an advanced CMOS process. Enhanced Features The V2751 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes in the ST16C2550 or one byte in the ST16C2450. The V2751 is designed to work with low supply voltage and high performance data communication systems, that require fast data processing time. Increased performance is realized in the V2751 by the larger transmit and receive FIFOs, FIFO trigger level control, FIFO level counters and automatic flow control mechanism. This allows the external processor to handle more networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the V2751, the data buffer will not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/ software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption. The V2751 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has to set FCTR Bit-3 to “1”. This pin is normally high for receive state, low for transmit state. Data Bus Interface, Intel or Motorola Type The 2751 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor (CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals change their functions depending on user’s selection, see pin description for details. The Intel and Motorola bus interface selection is made through the pin, 16/68#, pin 24. Data Rate The V2751 is capable of operation up to 4 Mbps at 3.3V with 16X internal sampling clock rate and 8 Mbps at 3.3V with 8X sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps. The rich feature set of the V2751 is available through the internal registers. Automatic hardware/software flow control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem interface controls, and a sleep mode are all standard features. Following a power on reset or an external reset, the V2751 is software compatible with previous generation of UARTs, 16C450, 16C550 and 16C650A as well as the 16C850. |
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