 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
XR16V2750 Datasheet(PDF) 3 Page - Exar Corporation |
|
||||||||||||||||||||||||||||||
XR16V2750 Datasheet(HTML) 3 Page - Exar Corporation |
|
|
3 / 52 page  XR16V2750 3 REV. 1.0.2 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PIN DESCRIPTIONS Pin Description NAME 32-QFN PIN # 48-TQFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 18 19 20 26 27 28 I Address data lines [2:0]. These 3 address lines select one of the inter- nal registers in UART channel A/B during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 2 1 32 31 30 29 28 27 3 2 1 48 47 46 45 44 I/O Data bus lines [7:0] (bidirectional). IOR# 14 19 I Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. IOW# 12 15 I Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. CSA# 7 10 I UART channel A select (active low) to enable UART channel A in the device for data bus operation. CSB# 8 11 I UART channel B select (active low) to enable UART channel B in the device for data bus operation. INTA 22 30 O UART channel A Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTA is set to the active mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is set to the three state mode and OP2A# output HIGH when MCR[3] is set to a logic 0 (default). See MCR[3]. INTB 21 29 O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# output HIGH when MCR[3] is set to a logic 0 (default). See MCR[3]. TXRDYA# - 43 O UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2. If it is not used, leave it unconnected. RXRDYA# - 31 O UART channel A Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel A. See Table 2. If it is not used, leave it unconnected. TXRDYB# - 6 O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See Table 3. If it is not used, leave it unconnected. |
Similar Part No. - XR16V2750_07 |
|
Similar Description - XR16V2750_07 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
