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MH32S72PHB-6 Datasheet(PDF) 12 Page - Mitsubishi Electric Semiconductor

Part No. MH32S72PHB-6
Description  2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32S72PHB-6 Datasheet(HTML) 12 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI
ELECTRIC
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72PHB-6
MITSUBISHI LSIs
12/May. /1999
MIT-DS-0318-0.0
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
12
R:Reserved for Future Use
/S
/RAS
/CAS
/WE
BA0,1 A11-0
CK
V
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
BT= 1
1
2
4
8
R
R
R
FP
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
0
0
WM
0
0
LTMODE
BT
BL
0
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
0
1
WRITE
MODE
BURST
SINGLE BIT
FP: Full Page


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