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SA572N Datasheet(PDF) 5 Page - NXP Semiconductors |
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SA572N Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 12 page Philips Semiconductors Product specification SA572 Programmable analog compandor 1998 Nov 03 5 SA572 BASIC APPLICATIONS Description The SA572 consists of two linearized, temperature-compensated gain cells ( ∆G), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.5V common bias reference derived from the power supply but otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows flexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements. Gain Cell Figure 4 shows the circuit configuration of the gain cell. Bases of the differential pairs Q1-Q2 and Q3-Q4 are both tied to the output and inputs of OPA A1. The negative feedback through Q1 holds the VBE of Q1-Q2 and the VBE of Q3-Q4 equal. The following relationship can be derived from the transistor model equation in the forward active region. DV BE Q3Q4 + D BE Q1Q2 (VBE = VT IIN IC/IS) V TIn 1 2 I G ) 1 2 I O I S * V TIn 1 2 I G * 1 2 I O I S where I IN + V IN R 1 R1 = 6.8kΩ I1 = 140µA I2 = 280µA V TIn I 1 ) IIN I S * V TIn I 2 * I1 * IIN I S (2) where I IN + V IN R 1 R1 = 6.8kΩ I1 = 140µA I2 = 280µA IO is the differential output current of the gain cell and IG is the gain control current of the gain cell. If all transistors Q1 through Q4 are of the same size, equation (2) can be simplified to: I O + 2 I 2 @ I IN @ IG * 1 I 2 I 2 * 2I1 @ I G (3) The first term of Equation 3 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The offset voltage can be trimmed out by feeding a current source within ±25µA into the THD trim pin. The residual distortion is third harmonic distortion and is caused by gain control ripple. In a compandor system, available control of fast attack and slow recovery improve ripple distortion significantly. At the unity gain level of 100mV, the gain cell gives THD (total harmonic distortion) of 0.17% typ. Output noise with no input signals is only 6 µV in the audio spectrum (10Hz-20kHz). The output current IO must feed the virtual ground input of an operational amplifier with a resistor from output to inverting input. The non-inverting input of the operational amplifier has to be biased at VREF if the output current IO is DC coupled. VREF THD TRIM V+ R1 6.8k 1 2 I G ) 1 2 I O I1 140 µA 280 µA I2 IG IO Q4 Q3 Q1 Q2 VIN + – A1 SR00697 Figure 4. Basic Gain Cell Schematic |
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