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MH32S72DBFA-6 Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor

Part No. MH32S72DBFA-6
Description  2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32S72DBFA-6 Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor

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2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72DBFA -6
30/Sep. /1999
MIT-DS-352-0.0
MITSUBISHI
ELECTRIC
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S0 - 3
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/W
Input
Combination of /RAS,/CAS,/W defines basic commands.
A0-11
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0-1
Input
Bank Address:BA0,1 is not simply BA.BA0,1 specifies
the bank to which a command is applied.BA must be set
with ACT,PRE,READ,WRITE commands
DQ0-63
CB0-7
Input/Output Data In and Data out are referenced to the rising edge
of CK
DQM0-7
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss
Power Supply Power Supply for the memory mounted module.
CK0
REGE
Output
Register enable:When REGE is low,All control signals and
address are buffered. (Buffer mode) When REGE is
high,All control and address are latched. (Latch mode)
4


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