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FSQ0365RL Datasheet(PDF) 12 Page - Fairchild Semiconductor |
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FSQ0365RL Datasheet(HTML) 12 Page - Fairchild Semiconductor |
12 / 24 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0365, FSQ0265, FSQ0165, FSQ321, FSQ311 Rev. 1.0.4 12 Functional Description 1. Startup: At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (Ca) connected to the Vcc pin, as illustrated in Figure 20. When VCC reaches 12V, the FPS begins switching and the internal high-voltage current source is disabled. The FPS continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless VCC goes below the stop voltage of 8V. Figure 20. Start-up Circuit 2. Feedback Control: FPS employs current mode control, as shown in Figure 21. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 2.1 Pulse-by-Pulse Current Limit: Because current mode control is employed, the peak current through the SenseFET is limited by the inverting input of PWM comparator (VFB*), as shown in Figure 21. Assuming that the 0.9mA current source flows only through the internal resistor (3R + R = 2.8k), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (VFB) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping VFB*. Therefore, the peak value of the current through the SenseFET is limited. 2.2 Leading Edge Blanking (LEB): At the instant the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. Figure 21. Pulse-Width-Modulation (PWM) Circuit 3. Synchronization: The FSQ-series employs a valley switching technique to minimize the switching noise and loss. The basic waveforms of the valley switching converter are shown in Figure 22. To minimize the MOSFET's switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value, as shown in Figure 22. The minimum drain voltage is indirectly detected by monitoring the VCC winding voltage, as shown in Figure 22. Figure 22. Valley Resonant Switching Waveforms 8V/12V V ref Internal Bias V CC V str I CH V CC good V DC C a FSQ0365RN Rev.00 2 5 3 OSC V CC V ref I delay I FB V SD R 3R Gate driver OLP D1 D2 + V FB* - V FB KA431 C B V O FOD817A R sense SenseFET FSQ0365RN Rev. 00 V DC V RO V RO V ds t F 0.7V V sync 300ns Delay 0.2V ON ON V ovp (6V) FSQ0365RN Rev.00 MOSFET Gate |
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