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MPC8541EVTALF Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC8541EVTALF Datasheet(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 84 page  MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4 24 Freescale Semiconductor Ethernet: Three-Speed, MII Management 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.3.1 MII Transmit AC Timing Specifications Table 22 provides the MII transmit AC timing specifications. Figure 9 shows the MII transmit AC timing diagram. Figure 9. MII Transmit AC Timing Diagram 8.2.3.2 MII Receive AC Timing Specifications Table 23 provides the MII receive AC timing specifications. Table 22. MII Transmit AC Timing Specifications At recommended operating conditions with LVDD of 3.3 V ± 5%. Parameter/Condition Symbol 1 Min Typ Max Unit TX_CLK clock period 10 Mbps tMTX 2 —400 — ns TX_CLK clock period 100 Mbps tMTX —40— ns TX_CLK duty cycle tMTXH/tMTX 35 — 65 % TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 1 5 15 ns TX_CLK data clock rise and fall time tMTXR, tMTXF 2,3 1.0 — 4.0 ns Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. Signal timings are measured at 0.7 V and 1.9 V voltage levels. 3. Guaranteed by design. TX_CLK TXD[3:0] tMTKHDX tMTX tMTXH tMTXR tMTXF TX_EN TX_ER |
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