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MPC5553MVM80 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC5553MVM80 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 66 page  Electrical Characteristics MPC5553 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11 3.7 Power-Up/Down Sequencing Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is nit used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).” Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33.” Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up/down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). 9 Preliminary value. Final specification pending characterization. Table 7. Power Sequence Pin Status for Fast Pads VDDE VDD33 VDD POR Pin Status for Fast Pad Output Driver pad_fc (fast) Low — — Asserted Low VDDE Low Low Asserted High VDDE Low VDD Asserted High VDDE VDD33 Low Asserted High impedance (Hi-Z) VDDE VDD33 VDD Asserted Hi-Z VDDE VDD33 VDD Negated Functional |
Similar Part No. - MPC5553MVM80 |
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Similar Description - MPC5553MVM80 |
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