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MH32S72AQJA-7 Datasheet(PDF) 16 Page - Mitsubishi Electric Semiconductor |
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MH32S72AQJA-7 Datasheet(HTML) 16 Page - Mitsubishi Electric Semiconductor |
16 / 56 page 2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM MH32S72AQJA-7, -8 17/Mar./2000 MIT-DS-0371-0.2 Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI LSIs MITSUBISHI ELECTRIC AC TIM ING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V CK Signal 1.4V 1.4V Any AC timing is referenced to the input signal crossing through 1.4V. LATCH MODE 16 Limits Symbol Parameter -7 Unit Min. Max. tCLK CK cycle time ns tCH CK High pulse width 3 10 ns tCL CK Low pilse width 3 ns tT Transition time of CK 1 10 ns tIS Input Setup time(all inputs) 2 ns tIH Input Hold time(all inputs) 1 ns tRC Row cycle time 70 ns tRCD Row to Column Delay 20 ns tRAS Row Active time 50 100000 ns tRP Row Precharge time 20 ns tWR Write Recovery time 20 ns tRRD Act to Act Deley time 20 ns tPDE Power Down Exit time 10 ns tRSC Mode Register Set Cycle time 20 ns tREF Refresh Interval time 64 ms CL=3 tSRX Self Refresh Exit time 10 ns -8 Min. Max. 3 13 3 1 10 2 1 70 20 50 100000 20 20 20 10 20 64 10 10 CL=4 10 ns |
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