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OXCFU950 Datasheet(PDF) 43 Page - Oxford Semiconductor |
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OXCFU950 Datasheet(HTML) 43 Page - Oxford Semiconductor |
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43 / 74 page  DS-0023 February 2007 External—Free Release Page 43 of 74 OXCFU950 DATA SHEET OXFORD SEMICONDUCTOR, INC. Register access notes: Note 0: Offset from function base address in I/O space Note 1: Requires LCR[7] = 0 Note 2: Requires ACR[7] = 0 Note 3: Requires that last value written to LCR was not 0xBF Note 4: To read this register ACR[7] must be = 0 Note 5: To read this register ACR[6] must be = 0 Note 6: Requires ACR[7] = 1 Note 7: Only bits 0 and 1 of this register can be written Note 8: To read this register ACR[6] must be = 1 Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set Note 10: TFL, RFL and GDS are available at two locations, accessing via the OXCFU950 specific register location being the most simple Note 11: The 32-bit FIFO Access registers can also be accessed at 0x00 through 0x03, when DBURST is set to 0x01. This is for systems where the UART must be mapped to an 8-byte address space. Register Name SPR Offset 12 R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Indexed Control Register Set ACR 0x00 R/W Additiona l Status Enable ICR Read Enable 950 Trigger Level Enable DTR definition and control AutoDSR Flow Control Enable Tx Disable Rx Disable CPR 0x01 R/W 5-bit integer part of clock prescaler 3-bit fractional part of clock prescaler TCR 0x02 R/W Unused 4 Bit N-times clock selection bits [3:0] 0x03 R/W Unused TTL 0x04 R/W Unused Transmitter Interrupt Trigger Level (0-127) RTL 0x05 R/W Unused Receiver Interrupt Trigger Level (1-127) FCL 0x06 R/W Unused Automatic Flow Control Lower Trigger Level (0-127) FCH 0x07 R/W Unused Automatic Flow Control Higher Trigger level (1-127) ID1 0x08 R Hardwired ID byte 1 (0x16) ID2 0x09 R Hardwired ID byte 1 (0xC9) ID3 0x0A R Hardwired ID byte 1 (0x50) REV 0x0B R Hardwired revision byte (0x0B) CSR 0x0C W Writing 0x00 to this register will reset the UART NMR 0x0D R/W Unused 9th Bit SChar 4 9th Bit Schar 3 9th Bit SChar 2 9th Bit SChar 1 9th-bit Int. En. 9 Bit Enable MDM 0x0E R/W Unused Disable wake-up sensitivity Δ DCD Wakeup disable Trailing RI edge disable Δ DSR Wakeup disable Δ CTS Wakeup disable RFC 0X0F R FiCR[7] FiCR[6] FiCR[5] FiCR[4] FiCR[3] FiCR[2] FiCR[1] FiCR[0] GDS13 0X10 R Unused Good Data Status DMS 0x11 R/W Force internal TxRdy inactive Force internal RxRdy inactive Unused Internal TxRdy status ( R ) Internal RxRdy status ( R ) PIDX 0x12 R Hardwired Port Index ( 0x00 ) 0x13 R/W Unused Table 17: Indexed Control Register Set |
Similar Part No. - OXCFU950_07 |
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Similar Description - OXCFU950_07 |
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