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MH32S72APHB-6 Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor

Part No. MH32S72APHB-6
Description  2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32S72APHB-6 Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor

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MH32S72APHB -6,-7,-8
2,415,919,104-BIT (33,554,432 - WORD BY 72-BIT)Synchronous DRAM
MITSUBISHI LSIs
(
/ 55 )
MITSUBISHI
ELECTRIC
17.Mar.2000
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0380-0.1
PIN FUNCTION
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
CKE0,1
Input
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
/S
(/S0~3)
Input
Chip Select: When /S is high,any command means
No Operation.
/RAS,/CAS,/WE
Input
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-9.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
DQ0-63
CB0-7
Input/Output Data In and Data out are referenced to the rising edge of
CK
DQMB0-7
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Vdd,Vss
Power Supply Power Supply for the memory mounted module.
SCL
SDA
SA0-3
Input
Output
Input
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
6
CK
(CK0 ~ CK3)


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