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PSMN005-55P Datasheet(PDF) 6 Page - NXP Semiconductors |
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PSMN005-55P Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 9 page Philips Semiconductors Product specification N-channel logic level TrenchMOS ™ transistor PSMN005-55B, PSMN005-55P Fig.13. Typical turn-on gate-charge characteristics. V GS = f(QG) Fig.14. Typical reverse diode current. I F = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.15. Maximum permissible non-repetitive avalanche current (I AS) versus avalanche time (tAV); unclamped inductive load 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 25 50 75 100 125 150 175 200 225 250 Gate charge, QG (nC) Gate-source voltage, VGS (V) ID = 75 A Tj = 25 C VDD = 11 V VDD = 44 V 1 10 100 0.001 0.01 0.1 1 10 Avalanche time, tAV (ms) Maximum Avalanche Current, IAS (A) Tj prior to avalanche = 150 C 25 C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0 20 40 60 80 100 IF/A VSDS/V Tj/C = 175 25 October 1999 6 Rev 1.200 |
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