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MH32D72AKLB-75 Datasheet(PDF) 16 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D72AKLB-75 Datasheet(HTML) 16 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0399-0.2
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
16
ABSOLUTE M AXIMUM RATINGS
DC OPERATING CONDITIONS
(Ta=0 ~ 70°C
, unless otherwise noted)
CAPACITANCE
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = Vss Q = 0V, unless otherwise noted)
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 3.7
V
VddQ
Supply Voltage for Output
with respect to VssQ
-0.5 ~ 3.7
V
VI
Input Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ
-0.5 ~ VddQ+0.5
V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25°C
W
Topr
Operating Temperature
0 ~ 70
Tstg
Storage Temperature
-40 ~ 100
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
Vdd/VddQ
Supply Voltage
2.3
2.5
2.7
V
VIH(DC)
High-Level Input Voltage
Vref + 0.18
VddQ+0.3
V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.18
V
Vref
Input Reference Voltage
1.15
1.35
V
1.25
VIN(DC)
Input Voltage Level, CK0 and /CK0
-0.3
VddQ + 0.3
V
VID(DC) Input Differential Voltage, CK0 and /CK0
0.36
VddQ + 0.6
V
VTT
I/O Termination Voltage
Vref - 0.04
V
Vref + 0.04
Notes
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
Tes t Condition
Limits(max.)
Unit
VI - 1.25V
f =100MHz
VI = 25mVrm
pF
pF
pF
pF
11.0
38.0
22.0
20
Notes
11
11
11
11
11.0
6
5
7
°C
°C


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