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MH32D72AKLB-75 Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLB-75 Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 40 page 
MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLB-75,-10 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0399-0.2 21.Mar.2001 Preliminary Spec. Some contents are subject to change without notice. 4 PIN FUNCTION CK0,/CK0 Input Clock: CK0 and /CK0 are diff erential clock inputs. All address and control input signals are sampled on the crossing of the positiv e edge of CK0 and negativ e edge of /CK0. Output (read) data is ref erenced to the crossings of CK0 and /CK0 (both directions of c rossing). CKE0, CKE1 Input Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the internal clock f or the f ollowing cyc le is ceased. CKE0 is also used to select auto / self ref resh. After self ref resh mode is started, CKE0 becomes asy nchronous input. Self ref resh is maintained as long as CKE0 is low. /S0, /S1 Input Phys ical Bank Select: When /S0,/S1 is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-11 Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specif ied by A0-11. The Column Address is specif ied by A0-9. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is perf ormed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input DQ 0-64 CB 0-7 Input / Output DQS0-8 Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. SYMBOL TYPE DESCRIPTION Input Vref Input SSTL_2 reference voltage. Vddspd Power Supply Power Supply for SPD RESET Input This signal is asy nchronous and is driv en low to the register in order to guarantee the register outputs are low. SDA Input / Output This bidirectional pin is used to transf er data into or out of the SPD EEPROM. A resistor must be connected f rom the SDA bus line to VDD to act as a pullup. SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected f rom the SCL bus time to VDD to act as a pullup. SA0-2 These signals are tied at the system planar to either VSS or VDD to conf igure the serial SPD EEPROM address range. Input VDD identif ication f lag VDDID DM0-8 Input / Output Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM. |
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