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MH32D72AKLB-75 Datasheet(PDF) 38 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D72AKLB-75 Datasheet(HTML) 38 Page - Mitsubishi Electric Semiconductor

 
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0399-0.2
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
38
EEPROM Components A.C. and D.C. Characteristics
Limits
Min.
Typ.
Max.
V
V
0
5.5
0
Supply Voltage
Supply Voltage
VCC
VSS
2.2
V
V
-1
Input High Voltage
Input Low Voltage
VIH
VIL
Symbol
Parameter
Units
Vccx0.3
Vccx0.7
V
Output Low Voltage
VOL
0.4
EEPROM A.C.Timing Parameters (Ta=0 to 70°C)
Limits
Min.
Max.
KHz
ns
200
100
4.7
SCL Clock Frequency
Noise Supression Time Constant at SCL, SDA inputs
fSCL
TI
us
us
4.7
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New
Transmission Can Start
TAA
TBUF
Symbol
Parameter
Units
4.0
us
Start Condition Hold Time
THD:STA
4.0
us
Clock Low Time
TLOW
4.7
us
Clock High Time
THIGH
0
us
Start Condition Setup Time
TSU:STA
250
us
Data In Hold Time
THD:DAT
ns
Data In Setup Time
TSU:DAT
us
SDA and SCL Rise Time
TR
ns
SDA and SCL Fall Time
TF
us
Stop Condition Setup Time
TSU:STO
4.0
ns
Data Out Hold Time
TDH
100
ms
Write Cycle Time
TWR
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
0
300
3.5
1
10
SCL
SDA
IN
TSU:STA
THD:STA
TF
TLOW
THIGH
TR
THD:DAT
TSU:DAT
TSU:STO
TBUF
SDA
OUT
TAA
TDH
Vcc+0.5


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