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MH32D72AKLB-75 Datasheet(PDF) 35 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D72AKLB-75 Datasheet(HTML) 35 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0399-0.2
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
35
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cy cle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK op eration during the power down mode.
/CLK
CLK
Power Down by CKE
Command
PRE
CKE
Command
ACT
CKE
Standby Power
Down
Active Power
Down
NOP
NOP
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM t o
write mask latency is 0.
Valid
NOP
NOP
Valid
tXPNR/
tXPRD
DM Function(BL=8,CL=2(Discrete))
Command
DQS
DQ
DM
Write
READ
D0
D1
D3
D4
D5
D6
D7
masked by DM=H
Don't Care
Q2
Q3
Q4
/CLK
CLK
Q0
Q1
Module input and output timing.


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