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MH32D72AKLB-75 Datasheet(PDF) 33 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLB-75 Datasheet(HTML) 33 Page - Mitsubishi Electric Semiconductor |
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33 / 40 page 
MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLB-75,-10 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0399-0.2 21.Mar.2001 Preliminary Spec. Some contents are subject to change without notice. 33 [S ELF REFRESH] Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD. Self-Refresh /RAS CKE /CS /CAS /WE A0-11 BA0,1 tXSNR Self Refresh Exit /CLK CLK X Y X Y tXSRD Act Read |
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