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MH32D72AKLB-75 Datasheet(PDF) 30 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D72AKLB-75 Datasheet(HTML) 30 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0399-0.2
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
30
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cy cle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
Write Interrupted by Write (BL=8)
Command
A0-9,11
A10
BA0,1
WRITE
Yi
0
00
WRITE
Yk
0
10
WRITE
Yj
0
00
WRITE
Yl
0
00
DQ
Dai1
Daj1
Daj3
Dak1
Dak3
Dak5
Dal1
DQS
Dal
2
Dal
3
Dal
5
Dal
6
Dal
7
Dal
4
Dal
0
Dak
4
Dak
2
Dak
0
Dai
0
Daj
0
Daj
2
/CLK
CLK
Module input and output timing.
Write Interrupted by Read (BL=8, CL=2.5(Discrete))
Command
A0-9,11
A10
BA0,1
DQ
WRITE
Yi
0
00
READ
Yj
0
00
Dai0
Dai1
Qaj0 Qaj1 Qaj2 Qaj3
QS
Qaj4 Qaj5 Qaj6 Qaj7
DM
tWTR
/CLK
CLK
Module input and output timing.


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