Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

MH32D72AKLB-75 Datasheet(PDF) 25 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLB-75
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Download  40 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
Logo 

MH32D72AKLB-75 Datasheet(HTML) 25 Page - Mitsubishi Electric Semiconductor

Zoom Inzoom in Zoom Outzoom out
 25 / 40 page
background image
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLB-75,-10
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0399-0.2
21.Mar.2001
Preliminary Spec.
Some contents are subject to change without notice.
25
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM , when the Burst
Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multip le banks. From the last
data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE
command, the auto-p recharge(WRITEA) is p erformed. Any command(READ,WRITE,PRE,ACT) to the
same bank is inhibited till the internal p recharge is comp lete. The next ACT command can be issued after
tDAL from the last input data cycle.
WRITE with Auto-Precharge (BL=8)
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
00
WRITE
1
00
ACT
Xb
00
tRCD
Da0
DQS
/CLK
CLK
Da1
Da2
Da3
Da4
Da5
Da6
Da7
tDAL
Xa
Y
Xb
Multi Bank Interleaving WRITE (BL=8)
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
00
WRITE
00
WRITE
0
0
10
ACT
Xb
10
0
10
tRCD
tRCD
PRE
Xa
0
00
PRE
DQS
/CLK
CLK
Da0
Da1
Da2
Da3
Da4
Da5
Da6
Da7
Db0
Db1
Db2 Db3
Db4
Db5
Db6
Db7
Xa
Ya
Yb
Xb
Module input and output timing.
Module input and output timing.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn