6

MC68EC030 TECHNICAL DATA

MOTOROLA

31

15

16

0

31

0

31

15

16

0

7

8

15

0

31

0

31

0

31

0

2

(CCR)

A7'

(ISP)

SR

VBR

SFC

DFC

A7"

(MSP)

CACR

CAAR

INTERRUPT

STACK POINTER

MASTER

STACK POINTER

STATUS

REGISTER

VECTOR

BASE REGISTER

ALTERNATE FUNCTION

CACHE CONTROL

REGISTER

CACHE ADDRESS

REGISTER

31

0

31

0

AC0

AC1

ACCESS CONTROL

REGISTER 0

ACCESS CONTROL

REGISTER 1

CODE REGISTERS

15

0

ACUSR

ACU STATUS

REGISTER

Figure 4. Supervisor Programming Model Supplement

The status register (see Figure 5) contains the interrupt priority mask (three bits) as well as the following

condition codes: extend (X), negate (N), zero (Z), overflow (V), and carry (C). Additional control bits

indicate that the controller is in the trace mode (T1 or T0), supervisor/user state (S), and master/interrupt

state (M).

T

S

III

X

N

Z

V

C

2

1

0

15

13

10

8

4

0

INTERRUPT

PRIORITY MASK

SYSTEM BYTE

USER BYTE

CONDITION

CODES

1

14

000

0

T0

M

1

12

11

9

765

32

EXTEND

NEGATIVE

ZERO

OVERFLOW

CARRY

TRACE ENABLE

SUPERVISOR/USER STATE

MASTER/INTERRUPT STATE

Figure 5. Status Register

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com