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56F8357 Datasheet(PDF) 78 Page - Freescale Semiconductor, Inc |
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56F8357 Datasheet(HTML) 78 Page - Freescale Semiconductor, Inc |
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78 / 177 page  56F8357 Technical Data, Rev. 15 78 Freescale Semiconductor Preliminary 5.4 Block Diagram Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ITCN is in this mode by default. • Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. Also, the IRQA and IRQB signals automatically become low-level sensitive in these modes even if the control register bits are set to make them falling-edge sensitive. This is because there is no clock available to detect the falling edge. A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. Priority Level 2->4 Decode INT1 Priority Level 2->4 Decode INT82 Level 0 82->7 Priority Encoder any0 Level 3 82->7 Priority Encoder any3 INT VAB IPIC CONTROL 7 7 PIC_EN IACK SR[9:8] |
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