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MH32D72AKLA-10 Datasheet(PDF) 24 Page - Mitsubishi Electric Semiconductor |
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MH32D72AKLA-10 Datasheet(HTML) 24 Page - Mitsubishi Electric Semiconductor |
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24 / 38 page 
MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 24 READ with Auto-Precharge (BL=8, CL=2(Discrete)) Command A0-9,11-12 A10 BA0,1 DQ ACT Xa Xa 00 READ Y 1 00 ACT Xb Xb 00 Internal precharge start (BL/2+1 in case of Module) tRCD tRP BL/2 + tRP BL/2 DQS /CLK CLK Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 READ Auto-Precharge Timing (BL=8) Command ACT READ DQ CL=2.5 BL/2 DQ CL=2 Qa0 /CLK CLK Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Module input and output timing. Module input and output timing. Discrete Internal Precharge Start Timing (In case of module, Precharge start at BL/2+1) CL=3.5 CL=3 Module |
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