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MH32D72AKLA-10 Datasheet(PDF) 22 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLA-10
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32D72AKLA-10 Datasheet(HTML) 22 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
22
A precharge command can be issued at BL/2(Discrete) from a read command without data loss.
Precharge all
Bank Activation and Precharge All (BL=8, CL=2 (Discrete level))
Command
A0-9,11-12
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
tRAS
tRP
tRCmin
2 ACT command / tRCmin
DQS
Qa0
BL/2
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four indep endent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD. M aximum 2 ACT commands
are allowed within tRC,although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Qa1
Qa2
Qa3
Qa4
Qa5
Qa6
Qa7
/CLK
CLK
Module input and output timing.


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