 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MH32D72AKLA-10 Datasheet(PDF) 13 Page - Mitsubishi Electric Semiconductor |
|
||||||||||||||||||||||||||||||
MH32D72AKLA-10 Datasheet(HTML) 13 Page - Mitsubishi Electric Semiconductor |
|
|
13 / 38 page  MITSUBISHI LSIs MITSUBISHI ELECTRIC MH32D72AKLA-10,-75 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0398-1.1 24.Nov.2000 Preliminary Spec. Some contents are subject to change without notice. 13 POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or multifunctioning. 1. Apply VDD before or the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL 4. Issue precharge command for all banks of the device 5. Issue EMRS 6. Issue MRS for the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable condition for 200 cycle After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks in discrete are in idle state. After tMRD from a MRS command, the DDR DIMM is ready for new command. R: Reserved for Future Use BL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Burst Length BT= 0 BT= 1 R 2 4 8 R R R R R 2 4 8 R R R R 0 1 Burst Type Sequential Interleaved A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA1 BA0 0 0 DR 0 LTMODE BT BL 0 0 0 /S0 /RAS /CAS /WE A11-A0 /CK0 V CK0 BA0 BA1 CL Latency Mode /CAS Latency R R 2 R R R 2.5 R 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 DLL Reset NO YES |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
