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MH32D72AKLA-10 Datasheet(PDF) 36 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLA-10
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32D72AKLA-10 Datasheet(HTML) 36 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
36
Serial Presence Detect Table I
Byte
Function described
SPD enrty data
SPD DATA(hex)
0
Number of Serial PD Bytes Written during Production
128
80
1
Total # bytes of SPD memory device
256 Bytes
08
2
Fundamental memory type
SDRAM DDR
07
3
# Row Addresses on this assembly
12
4
# Column Addresses on this assembly
11
5
# Module Banks on this assembly
1BANK
01
6
Data Width of this assembly...
x72
48
7
... Data Width continuation
0
00
8
Voltage interface standard of this assembly
SSTL2.5V
04
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=2.5
10
SDRAM Access from Clock
tAC for CL=2.5
11
DIMM Configuration type (Non-parity,Parity,ECC)
ECC
02
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
x4
04
14
Error Checking SDRAM data width
x4
04
15
MIimum Clock Delay, Random Column Access
01
16
Burst Lengths Supported
2, 4, 8
0E
17
Number of Device Banks
4bank
04
18
CAS# Latency
2.0, 2.5
0C
19
CS# Latency
20
WE Latency
21
SDRAM Module Attributes
Registered with PLL
26
22
SDRAM Device Attributes:General
VDD + 0.2V
00
23
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
24
SDRAM Access form Clock(2nd highest CAS latency)
80
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
26
SDRAM Access form Clock(3rd highest CAS latency)
27
Minimum Row Precharge Time (tRP)
15ns
50
28
Minimum Row Active to Row Active Delay (tRRD)
20ns
3C
8.0ns
-10
10ns
A0
75
-75
29
RAS to CAS Delay Minv (tRCD)
20ns
2D
30
Active to Precharge Min (tRAS)
32
7.5ns
+0.75ns
+0.8 ns
-75
-10
-75
-10
-75
-10
Undefined
-75
-10
45ns
50ns
+0.75ns
+0.8ns
Differential Clock
0C
0B
75
80
75
80
00
50
15.625uS/SR
80
0
1
02
01
1 clock
10ns
A0
-75
-10
-75
-10
Undefined
Undefined
Undefined
00
00
00


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