MH32D72AKLA-10 datasheet(33/38 Pages) MITSUBISHI | 2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Part No.	MH32D72AKLA-10

Description	2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

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33 / 38 page

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

MH32D72AKLA-10,-75

2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MIT-DS-0398-1.1

24.Nov.2000

Preliminary Spec.

Some contents are subject to change without notice.

33

[Asynchronous S ELF REFRESH]

Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command

(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept

low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs

including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.

To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then

asserting CKE for longer than tXSNR/tXSRD.

Asynchronous Self-Refresh

/RAS

CKE

/CS

/CAS

/WE

A0-12

BA0,1

tXSNR

Self Refresh Exit

max 2 tCLK

/CLK

CLK

Act

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