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MH32D72AKLA-10 Datasheet(PDF) 31 Page - Mitsubishi Electric Semiconductor

Part # MH32D72AKLA-10
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32D72AKLA-10 Datasheet(HTML) 31 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
31
[Initialize and Mode Register sets]
Command
/CLK
CLK
EMRS
PRE
NOP
MRS
PRE
AR
AR
MRS
ACT
Code
Code
Xa
Code
Xa
1 0
Xa
A0-9,11,12
A10
Code
1
BA0,1
DQS
DQ
1
0 0
0 0
Code
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Auto-Refresh
/RAS
CKE
/CS
/CAS
/WE
A0-12
BA0,1
NOP or DESELECT
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
/CLK
CLK
Code
Single cy cle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally . 4096 REFA cy cles within 64ms refresh 128M bits memory cells.
The auto-refresh is p erformed on 4 banks concurrently . Before p erforming an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.


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