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MH32D72AKLA-10 Datasheet(PDF) 26 Page - Mitsubishi Electric Semiconductor

Part No. MH32D72AKLA-10
Description  2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

MH32D72AKLA-10 Datasheet(HTML) 26 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH32D72AKLA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0398-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
26
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency . As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examp les of BL=8.
Read Interrupted by Precharge (BL=8)
CL=2.5
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
Read Interrupted by Read (BL=8, CL=2(Discrete))
Command
A0-9,11
A10
BA0,1
DQ
Yi
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
DQS
Qai0 Qai1 Qaj0 Qaj1
Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2
Qal3 Qal4 Qal5 Qal6 Qal7
/CLK
CLK
/CLK
CLK
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
READ
READ
PRE
READ PRE
DQS
DQS
Module input and output timing.
Module input and output timing.
Discrete
CL=3.5
Module


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