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MH32D64KQH-75 Datasheet(PDF) 19 Page - Mitsubishi Electric Semiconductor |
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MH32D64KQH-75 Datasheet(HTML) 19 Page - Mitsubishi Electric Semiconductor |
19 / 40 page MH32D64KQH-75,-10 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module MIT-DS-0417-0.2 17.May.2001 Preliminary Spec. Some contents are subject to change without notice. MITSUBISHI LSIs MITSUBISHI ELECTRIC 19 18 17 7.8 7.8 1 1 1 1 200 200 80 75 1 1 15 15 15 15 20 20 20 20 80 75 70 65 120,000 50 120,000 45 us tCK tCK tCK ns tCK ns ns ns ns ns Average Periodic Refresh interval tREFI Exit Power down to -Read command tXPRD Exit Power down to command tXPNR tXSRD Exit Self Ref. to -Read command tXSNR Exit Self Ref. to non-Read command tWTR Internal Write to Read Command Delay ns 35 35 Auto Precharge write recovery + precharge time tDAL -10 -75 AC Characteristics Max. Min. Max. Min. Parameter tWR Write Recovery time tRRD Act to Act Delay time Row Precharge time Row to Column Delay tRP tRCD tRFC Auto Ref. to Active/Auto Ref. command period ns Row Cycle time(operation) tRC Row Active time ns tRAS Notes Unit Symbol Output Load Condition (f or component measurement) DQ Output Timing Measurement Reference Point VREF VREF DQS VOU VREF 30pF 50ohm VTT =V REF Zo=50 ohm AC TIMING REQUIREMENTS(Continues) (Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted) |
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