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MH32D64KQH-75 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part No. MH32D64KQH-75
Description  2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D64KQH-75 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor

 
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MH32D64KQH-75,-10
2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0417-0.2
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
1
DESCRIPTION
APPLICATION
Main memoryunit for Note PC, Mobile etc.
FEATURES
Type name
133MHz
MH32D64KQH-10
MH32D64KQH-75
Max.
Frequency
100MHz
The MH32D64KQH is 33554432 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 8 industry standard 32M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
(Front)
(Back)
1
2
199
200
PCB Outline
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
- 200pin SO-DIMM
-
Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cyc le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Diff erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address
,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cyc les /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration


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