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MH32D64AKQJ-75 Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor

Part No. MH32D64AKQJ-75
Description  2,147,483,684-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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MH32D64AKQJ-75 Datasheet(HTML) 3 Page - Mitsubishi Electric Semiconductor

 
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MH32D64AKQJ-75,-10
2,147,483,684-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0422-0.0
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
3
Block Diagram
/CK0
SERIAL PD
SCL
SDA
A0
A1
A2
Vdd
Vss
D0 - D7
D0 - D7
/S0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
CKE0
D0 - D3
/RAS
D0 - D7
/CAS
D0 - D7
/WE
D0 - D7
BA0,BA1,A<12:0>
D0 - D7
CK0
22
I/O 0
I/O 1
I/O 2
I/O 3
/S
D0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
D2
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
/S
D1
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
D3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
/S
D4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
/S
D5
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
D6
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 0
I/O 1
I/O 2
I/O 3
D7
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/S1
4loads
CKE1
D4 - D7
UDM
DQS1
UDQS
DM1
LDM
DQS0
LDQS
DM0
UDM
UDQS
LDM
LDQS
/S
LDM
DQS4
LDQS
DM4
LDM
LDQS
/S
UDM
DQS5
UDQS
DM5
UDM
UDQS
LDM
DQS2
LDQS
DM2
LDM
LDQS
UDM
DQS3
UDQS
DM3
UDM
UDQS
/S
/S
/S
LDM
DQS6
LDQS
DM6
LDM
LDQS
UDM
DQS7
UDQS
DM7
UDM
UDQS
VddSPD
SPD
Vref
D0 - D7
VddID
SA0
SA1
SA2
WP
/CK1
CK1
4loads
/CK2
CK2
0loads
NOTE: DQ wiring may differ from that
described in this drawing; however
DQ/DM/DQS relationships are
maintained as shown.
Vdd ID strap connections:
(for memory device Vdd, VddQ)
Strap out (open): Vdd=VddQ
Strap in (closed): Vdd=VddQ


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