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PLC18V8ZIADB Datasheet(PDF) 5 Page - NXP Semiconductors |
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PLC18V8ZIADB Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 23 page Philips Semiconductors Product specification PLC18V8Z Zero standby power CMOS versatile PAL devices 1997 Aug 08 5 LOGIC DIAGRAM Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direc- tion term. Denotes a programmable cell location. 1 2 3 4 5 6 7 8 9 NOTES: In the unprogrammed or virgin state: All cells are in a conductive state. All AND gate locations are pulled to a logic “0” (Low). Output polarity is inverting. 0 4 8 12 162024 2832 35 SP AR CLK OE AC1 AC2 DIR CLK F7 19 11 SP AR CLK OE AC1 AC2 DIR F6 18 SP AR CLK OE AC1 AC2 DIR F5 17 SP AR CLK OE AC1 AC2 DIR F4 16 SP AR CLK OE AC1 AC2 DIR F3 15 SP AR CLK OE AC1 AC2 DIR F2 14 SP AR CLK OE AC1 AC2 DIR F1 13 SP AR CLK OE AC1 AC2 DIR F0 12 SP AR I9/OE I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 CONFIG. CELL SP00012 |
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