Philips Semiconductors Programmable Logic Devices

Product specification

PLUS173B/D

Programmable logic arrays

(22

× 42 × 10)

October 22, 1993

37

AC ELECTRICAL CHARACTERISTICS

0

LIMITS

SYMBOL

PARAMETER

FROM

TO

TEST

PLUS173B

PLUS173D

UNIT

CONDITION

MIN

TYP

MAX

MIN

TYP

MAX

Input +/–

Output +/–

11

15

10

12

ns

Input +/–

Output –

11

15

10

12

ns

Input +/–

Output +

11

15

10

12

ns

NOTES:

2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORM

MEASUREMENTS:

All circuit delays are measured at the +1.5V level

of inputs and outputs, unless otherwise specified.

90%

10%

5ns

5ns

5ns

5ns

90%

10%

+3.0V

+3.0V

0V

0V

tR

tF

Input Pulses

TIMING DEFINITIONS

SYMBOL

PARAMETER

Propagation delay between

input and output.

Delay between input change

and when output is off (Hi-Z

or High).

Delay between input change

and when output reflects

specified output level.

TEST LOAD CIRCUIT

TIMING DIAGRAM

Test Load Circuit

+5V

CL

R1

R2

S1

GND

BZ

BZ

INPUTS

In

In

BM

BM

OUTPUTS

C2

C1

DUT

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

+3V

0V

VOH

VOL

I, B

B

tPD

1.5V

1.5V

1.5V

1.5V

1.5V

tOD

tOE

VT