PLC42VA12A datasheet(6/20 Pages) PHILIPS

Part #	PLC42VA12A

Description	CMOS programmable multi-function PLD 42 횞 105 횞 12

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors Programmable Logic Devices

Product specification

PLC42VA12

CMOS programmable multi-function PLD

(42

× 105 × 12)

October 22, 1993

78

DC ELECTRICAL CHARACTERISTICS

0

°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V

LIMITS

SYMBOL

PARAMETER

TEST CONDITION

MIN

TYP1

MAX

UNIT

Input voltage2

VIL

Low

VCC = MIN

–0.3

0.8

V

VIH

High

VCC = MAX

2.0

VCC + 0.3

V

Output voltage2

VOL

Low

VCC = MIN; IOL = 16mA

0.3

0.5

V

VOH

High

VCC = MIN; IOH = –3.2mA

2.4

4.3

V

Input current

IIL

Low

VIN = GND

–1

–10

µA

IIH

High

VIN = VCC

+1

10

µA

Output current

IO(OFF)

Hi-Z state

VOUT = VCC

VOUT = GND

1

–1

10

–10

µA

IOS

Short-circuit3,7

VOUT = GND

–130

mA

ICC1

VCC supply current (Active)4

IOUT = 0mA, f = 15MHz6, VCC = MAX

90

120

mA

ICC2

VCC supply current (Active)5

IOUT = 0mA, f = 15MHz6, VCC = MAX

70

100

mA

Capacitance

CI

Input

VCC = 5V; VIN = 2.0V

12

pF

CB

I/O

VB = 2.0V

15

pF

NOTES:

1. All typical values are at VCC = 5V. Tamb = +25°C.

2. All voltage values are with respect to network ground terminal.

3. Duration of short–circuit should not exceed one second. Test one at a time.

4. Tested with VIL = 0.45V, VIH = 2.4V.

5. Tested with VIL = 0V, VIH = VCC.

6. Refer to Figure 1,

∆ICC vs Frequency (worst case). (Referenced from 15MHz)

The ICC increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz.

The ICC remains at a worst case for the frequency range of 26MHz up to 37MHz.

The ICC decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz.

The worst case ICC is calculated as follows:

–

All dedicated inputs are switching.

–

All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling.

–

All 12 outputs are disabled.

–

The number of product terms connected does not impact the ICC.

7. Refer to Figure 2 for

∆tPD vs output capacitance loading.

Figure 1.

∆ICC vs Frequency

(Worst Case) (Referenced from 15MHz)

Figure 2.

∆tPD vs Output

Capacitance Loading (Typical)

f(MHz)

+25

+10

–5

–10

–15

1

5

10

15

20

25

30

6

5

4

3

2

1

0

–1

–2

0

20

40

60

80 100 120 140 160 180 200

OUTPUT CAPACITANCE LOADING (pF)

35

40

0

+5

+15

+20

+30

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